1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method for determining the reliability of dielectric layers.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability, performance and throughput and to reduce the cost of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
By way of background, FIG. 1 depicts an illustrative transistor 10 that may be found in many modern integrated circuit devices. The transistor 10 is formed above a substrate 12 and it is generally comprised of a dielectric layer 14, a gate electrode 16, sidewall spacers 18 and source/drain regions 20. The substrate 12 may be a bulk semiconductor substrate, or it may be a silicon-on-insulator (SOI) substrate. An isolation region 22 is typically established around the transistor 10 to electrically isolate it from other transistors formed on the substrate 12. A layer of insulating material 15, e.g., silicon dioxide, is formed above the substrate 12, and conductive contacts 17 are provided to the source and drain regions 20. A contact 19 is also provided to the gate electrode 16. However, in an actual device, the gate contact 19 may not be in the same plane as the source/drain contacts 17, as indicated in FIG. 1. Nevertheless, FIG. 1 is provided to describe an illustrative example of a prior art transistor 10. Typically, a modern integrated circuit device, such as a microprocessor, may be comprised of millions of transistors 10 like the one depicted in FIG. 1. Additionally, a completed device may have many additional metallization layers formed above the transistors. Another illustrative conductive interconnection level of metal line 17A is formed in the dielectric layer 15A. The exact configuration of these multiple layers of metal may vary depending on the particular application. However, it should be understood that a completed integrated circuit device may be comprised of many interlevel and intralevel dielectric layers having conductive lines and vias formed therein.
As set forth previously, there is a constant drive within the industry to increase the performance capability of integrated circuit devices. To that end, great efforts have been made to increase the performance capability of such transistors 10. All other things being equal, the smaller the gate length of the transistor 10, the faster it will operate. Current-day, cutting-edge integrated circuit devices employ transistors 10 having a gate length on the order of approximately 0.06–0.08 μm, and further reductions in the gate length are planned in the future. However, the drive to increase the performance capabilities of the transistor 10 has also necessitated changes in other components of the transistor 10 as well. For example, all other things being equal, the thinner the dielectric layer 14, the faster the transistor 10 will operate. Typically, for current high speed transistor design, the dielectric layer 14 may have a thickness that ranges from approximately 1.5 nm and less, and further reductions are planned in the future. Moreover, there is great deal of investigation into alternative materials and methods of making dielectric layers such that improved performance capabilities may be realized. Typically, the dielectric layer 14 will be made from a material such as silicon dioxide, or a layer of silicon dioxide having an enhanced nitrogen concentration. There is also investigation into using various so-called “high-k” dielectric materials for the dielectric layer, e.g., dielectric layers having a dielectric constant greater than 5.
Given the importance of dielectric layers with respect to performance of the completed device, there has always been great interest in ensuring that high quality, reliable dielectric layers 14 can be manufactured for use in such applications. To that end, typically, semiconductor device manufacturers conduct many tests in an effort to determine and ensure the reliability of such dielectric layers. One such test attempts to evaluate the qualities and capabilities of the dielectric layers 14 by subjecting the dielectric layer 14 to a constant voltage over a relatively long period of time until a relatively sharp increase in gate current (Ig) can be detected, i.e., the so-called breakdown point of the dielectric layer 14. This testing is generally known as time-dependent dielectric breakdown (TDDB) testing. Using this methodology, a relatively low voltage, e.g., on the order of approximately 3 volts, may be constantly applied to the gate electrode, and the gate current may be constantly monitored to determine when breakdown has occurred. Such testing is normally performed on hundreds, if not thousands, of test structures. Unfortunately, such testing can take a very long time, e.g., on the order of several weeks or two-three months, to complete due to the time it takes for the dielectric layers to actually reach the breakdown point. The results of such tests are typically analyzed using known statistical techniques to determine the reliability and quality of the dielectric layer. Dielectric layers may also be subjected to additional testing to further evaluate the quality of the dielectric, such as, for example, area scaling, voltage scaling, temperature scaling, etc.
Unfortunately, as the thickness of the dielectric layer 14 continues to decrease, the traditional TDDB methodology of testing for breakdown of the dielectric layer 14 has proven to be less effective than desirable. That is, for very thin dielectric layers, e.g., on order of approximately 3.0 nm and less, there is a phenomenon known as the soft breakdown that makes it very difficult to detect exactly when breakdown of the dielectric layer 14 occurs. Dielectric breakdown is associated with an increase in gate current, i.e., a current that flows from the gate electrode 16 and through the dielectric layer 14. For very thin dielectric layers, e.g., less than or equal to approximately 3.0 nm, the gate leakage current operates via a direct tunneling mechanism. Thus, there is no longer a clear time-to-breakdown (TBD) point in the gate current (Ig) degradation curve for such thin dielectric layers. However, time-to-breakdown (TBD) is the most important parameter for a given voltage. Of course, the prior art method of using constant voltage TDDB methodologies can still be employed on very thin dielectric layers, but the time at which the dielectric layer begins to degrade is difficult to detect using such methodologies because of the soft breakdown phenomenon described above.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.